Extracting VDD/VSS Nets for Impedance Simulation

Steve DiBartolomeo
Applications Manager
Artwork Conversion Software, Inc.

An interesting application of NETEX is the extraction of large power and ground nets from a chip's layout data (GDSII). Artwork was asked to help extract the VDD and VSS nets from a high speed chip so that these nets could be analyzed and the dynamic impedance between the power/ground connections and the circuits sinking the power/ground could be simulated.

top view of flip chip (bump pads in black)

The chip is a flip chip design where the power, ground and signals flow into the chip from the surface through “bump” pads.

Because modern chips process signals with extremely high frequencies, the assumption that power and ground nets have essentially zero impedance is no longer valid; accurately estimating the impedance is important to understanding how signal crosstalk and noise can propagate on the power/ground nets.

In priniciple, the same field analysis that is commonly done on signal nets can be applied to power and ground nets. In practice the size and complexity of the nets combined with the size of the IC layout data requires some tricky extraction processes prior to any simulation.

crossection of the chip - power and ground attach at the top through solder bumps and the circuits (designed on M1 and M2) get their power/ground from M3.

NETEX to the Rescue

Artwork has previous experience in extracting complex nets from extremely large GDSII databases and in fact developed a program, NETEX, several years ago specifically targeted with clock net extraction from state-of-the-art CPU designs.

NETEX reads the GDSII layout together with a “stack up” technology file and a configuration file; it uses boolean operations to determine which conductors are touching. All touching or overlapping conductors are booleanized and saved as a separate database structure.

It makes no difference to NETEX whether it is extracting a clock net or a VDD net -- the approach is the same.

Additional Database Reduction

In addition to extracting the VDD/VSS nets, we also attack and solve the problem of simulating arrays of vias. This design (as do most IC layouts) uses arrays of vias to handle high current. These large arrays cause a simulator to run very slowly or possibly not to complete a simulation at all. By using a sizing and boolean operation we are able to merge large arrays of vias into a single large rectangle. The simulation engineer can make the required compensation for metal density and get an accurate result.

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